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APPLICATION NOTE
SH7137 Group
MTU2: Output of Complementary Pairs of PWM Signals in Three Phases (Complementary PWM Mode)
Introduction
This application note describes an example of setting up multi-function timer pulse unit 2 (MTU2) for the output of complementary pulse width modulation (PWM) waveforms in three phases with a non-overlapping relationship between states of the positive and inverse signals.
Target Device
SH7137
Contents
1. 2. 3. Preface .............................................................................................................................................. 2 Description of the Sample Application .............................................................................................. 3 Documents for Reference ............................................................................................................... 22
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MTU2: Output of Complementary Pairs of PWM Signals in Three Phases (Complementary PWM Mode)
1. 1.1
Preface Specifications
The sample program employs MTU2 in complementary PWM mode for the three-phase output of complementary PWM waveforms. Figure 1 shows an overview. 1. Channels 3 and 4 of MTU2 are used to make settings for complementary PWM mode (complementary PWM mode 3). The output pins for the positive PWM signals are TIOC3B, TIOC4A, and TIOC4B. The corresponding inverse signals are output on pins TIOC3D, TIOC4C, and TIOC4D. The low level is selected as active for PWM output. 2. For both the positive and inverse signals, MTU2 outputs PWM waveforms with a dead time (interval for preventing short-circuits) in which the state transitions of the positive and inverse signals do not overlap. The duration of the dead time is set to 4 s. 3. PWM carrier cycle is set to 400 s. 4. The PWM duty cycle is incremented or decremented by an interrupt signal generated every PWM cycle. 5. Waveforms are output by toggling the level on the TIOC3A pin in synchronization with half cycles of the PWM carrier.
SH7137 Interrupt request SH-2A Channels 3 and 4 Complementary PWM mode 3 MTU2 TIOC3A(PE8) TIOC3B (PE9) TIOC3D (PE11) TIOC4A (PE12) TIOC4C (PE14) TIOC4B (PE13) TIOC4D (PE15) Output toggled (synchronized with PWM cycle) PWM output pin 1 (positive phase) PWM output pin 1' (inverse phase) PWM output pin 2 (positive phase) PWM output pin 2' (inverse phase) PWM output pin 3 (positive phase) PWM output pin 3' (inverse phase)
PWM cycle setting PWM duty setting (x 3) Dead time setting
Figure 1 Three-Phase Output of Complementary PWM (Complementary PWM Mode 3)
1.2
Module Used
Channels 3 and 4 of MTU2
1.3
Table 1
Applicable Conditions
Applicable Conditions Description SH7137 [R5F7137] Internal clock: I = 80 MHz Bus clock: B = 40 MHz Peripheral clock: P = 40 MHz MTU2S clock: MP = 40 MHz AD clock: MI = 80 MHz Single-chip SuperH RISC engine C/C++ Compiler Ver.9.02.00 from Renesas Technology Default settings of the C compiler
Item MCU Operating frequency
MCU operating mode Compiler C compiler options
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MTU2: Output of Complementary Pairs of PWM Signals in Three Phases (Complementary PWM Mode)
2.
Description of the Sample Application
In this sample program, MTU2 is used in complementary PWM mode.
2.1
2.1.1
Operational Overview of Module Used
Multi-Function Timer Pulse Unit 2 (MTU2)
MTU2 is a multi-functional timer unit that has six 16-bit timer channels. Settings for compare-match function, inputcapture function, etc. can be made for each channel. Settings for complementary PWM mode and reset-synchronized PWM mode are made for channels 3 and 4, enabling the control of six PWM output lines. For details on MTU2, see the section on MTU2 in the SH7137 Group Hardware Manual (REJ09B0402). Table 2 gives an overview of MTU2 and figure 2 is a block diagram of MTU2. Table 2 Overview of MTU2 Description 16-bit timer x 6 channels (channels 0 to 5) The clock signal for counter input can be selected from among 8 different input clock signals (except for channel 5, with only 4 different clock signals available). * * * * * * * * * Waveform output on compare match Input capture function Counter clearing Simultaneous writing to multiple timer counters (TCNT) Simultaneous clearing by compare match and input capture Input to and output from registers are synchronized with counter operation. PWM output in up to 12 phases in combination with synchronous operation A/D converter start trigger can be generated. In complementary PWM mode, interrupts at the crest and trough of the counter value and A/D converter start triggers can be skipped.
Item Number of channels Counter clock Operation of channels 0 to 5
Triggers for A/D converter
Buffered operation Operating modes
Interrupt requests Others
* Settings for buffered operation of registers can be made to channels 0, 3, and 4. * Settings for PWM mode can be made on channels 0 to 4. * Settings for phase counting mode can be set for each of channels 1 and 2 individually. * Waveform output in a total of six phases, including the positive and inverse signals for three phases, is possible in reset-synchronized PWM mode or complementary PWM mode. * 28 different interrupt sources (interrupt generation by compare match, input capture, etc.) * Cascade-connection operation * High-speed access by internal 16-bit bus * Automatic transfer of register data is enabled. * Module standby mode can be set. * Dead time compensation counter is available in channel 5.
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MTU2: Output of Complementary Pairs of PWM Signals in Three Phases (Complementary PWM Mode)
TIORL
TMDR
Channel 3
TSR
TGRC
TGRD
TGRA
TGRB
TCNT
Input/output pins Channel 3: TIOC3A TIOC3B TIOC3C TIOC3D Channel 4: TIOC4A TIOC4B TIOC4C TIOC4D
Control logic for channels 3 and 4
Interrupt request signals Channel 3: TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 Channel 4: TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4
TIORH TIORL
TMDR
Channel 4
TSR
TIER
TCR
TIORH
TOCR
TGCR
TIER
TCR
TCNTS
TCDR
Channel 2
TGRA
TGRB
TCNT
Clock input Internal clock: MP/1 MP/4 MP/16 MP/64 MP/256 MP/1024 External clock: TCLKA TCLKB TCLKC TCLKD
Control logic for channels 0 to 2
Module data bus
Input pins Channel 5: TIC5U TIC5V TIC5W
Channel 5
TOER
TDDR TCNTW
TCBR
TGRC
TGRD
TGRA
TGRB
TCNT
Channel 5: TGIU_5 TGIV_5 TGIW_5
TCNTU
TCNTV
TGRW
TGRU
TGRV
TIOR
TIER
TCR
TSR
Control logic
Common
TSYR
Internal data bus
BUS I/F
TMDR
TSR
A/D conversion start signals Channels 0 to 4: TRGAN Channel 0: TRG0N Channel 4: TRG4AN TRG4BN
TSTR
TIORL
TMDR
Input/output pins Channel 0: TIOC0A TIOC0B TIOC0C TIOC0D Channel 1: TIOC1A TIOC1B Channel 2: TIOC2A TIOC2B
TIORH
Interrupt request signals Channel 0: TGIA_0 TGIB_0 TGIC_0 TGID_0 TGIE_0 TGIF_0 TCIV_0 Channel 1: TGIA_1 TGIB_1 TCIV_1 TCIU_1 Channel 2: TGIA_2 TGIB_2 TCIV_2 TCIU_2
TIOR
TMDR
Channel 1
TSR
TIER
TCR
TIOR
Channel 0
TSR
TIER
TCR
TGRA
TGRB TGRC
TCNT
TGRD
TGRA
TGRB
TGRE
[Legend] TSTR: Timer start register TSYR: Timer synchronous register TCR: Timer control register TMDR: Timer mode register TIOR: Timer I/O control register TIORH: Timer I/O control register H TIORL: Timer I/O control register L TIER: Timer interrupt enable register TGCR: Timer gate control register TOER: Timer output master enable register TOCR: Timer output control register TSR: Timer status register TCNT: Timer counter TCNTS: Timer subcounter TCDR: TCBR: TDDR: TGRA: TGRB: TGRC: TGRD: TGRE: TGRF: TGRU: TGRV: TGRW: Timer cycle data register Timer cycle buffer register Timer dead time data register Timer general register A Timer general register B Timer general register C Timer general register D Timer general register E Timer general register F Timer general register U Timer general register V Timer general register W
Figure 2 Block Diagram of MTU2
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TIER
TCR
June 2009
TGRF
TCNT
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MTU2: Output of Complementary Pairs of PWM Signals in Three Phases (Complementary PWM Mode)
2.1.2
Complementary PWM Mode
Setting for complementary PWM mode can be made by the combination of channels 3 and 4 of MTU2. In complementary PWM mode, PWM waveforms are output in three phases with a non-overlapping relationship between the states of the positive and inverse signals. The output of PWM waveforms which do not have the non-overlapping time (interval for preventing short circuits) can also be set up. PWM output pins for complementary PWM mode are pins TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D. Furthermore, toggling of the output level in synchronization with the PWM cycle can be set up on the TIOC3A pin. Figure 3 is a block diagram of channels 3 and 4 of MTU2 in complementary PWM mode.
TCNT_4 underflow interrupt
TGRA_3 comparematch interrupt
TGRC_3
TCBR
TDDR
TGRA_3
TCDR
Comparator
Output controller
Match signal
PWM cycle output PWM output 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6 External cutoff input POE0 POE1 POE2
Comparator
Match signal
TGRB_3
TGRA_4
TGRD_3
TGRC_4
TGRD_4
TGRB_4
Temp 2
Temp 3
Temp 1
External cutoff interrupt
: Registers that can always be read or written from the CPU : Registers that can be read or written from the CPU (but for which access disabling can be set by TRWER) : Registers that cannot be read or written from the CPU (except for TCNTS, which can only be read)
Figure 3 Block Diagram of Channels 3 and 4 in Complementary PWM Mode
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Output protection circuit
TCNT_3
TCNTS
TCNT_4
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MTU2: Output of Complementary Pairs of PWM Signals in Three Phases (Complementary PWM Mode)
The followings are register functions of channel 3 and 4 when complementary PWM mode is set. * Timer general register A_3 (TGRA_3) TGRA_3 functions as a compare match register. The upper limit (1/2 carrier cycle + dead time) for counting is set here. Moreover, when the value in this register is changed during timer operation, the new value is that set in timer general register C_3 (TGRC_3). * Timer general register B_3 (TGRB_3) TGRB_3 functions as a comparison register. The duty cycle of the PWM waveforms which are output from pins TIOC3B and TIOC3D is set by the values in this register. Moreover, when the value in this register is changed during timer operation, the new value is that set in timer general register D_3 (TGRD_3). * Timer general register C_3 (TGRC_3) TGRC_3 functions as the buffer register for TGRA_3. During timer operation, the values set in this register are written to TGRA_3. * Timer general register D_3 (TGRD_3) TGRD_3 functions as the buffer register for TGRB_3. During timer operation, the values set in this register are written to TGRB_3. * Timer general register A_4 (TGRA_4) TGRA_4 functions as a comparison register. The duty cycle of PWM the waveforms which are output from pins TIOC4A and TIOC4C are set in this register. Moreover, when the value in this register is changed during timer operation, the value is that set in the timer general register C_4 (TGRC_4). * Timer general register B_4 (TGRB_4) TGRB_4 functions as a comparison register. The duty cycle of the PWM waveforms which are output from pins TIOC4B and TIOC4D are set in this register. Moreover, when the value in this register is changed during timer operation, the value to be changed is set in the timer general register D_4 (TGRD_4). * Timer general register C_4 (TGRC_4) TGRC_4 functions as a buffer register for TGRA_4. During timer operation, the values set in this register are written to TGRA_4. * Timer general register D_4 (TGRD_4) TGRD_4 functions as a buffer register for TGRB_4. During timer operation, the values set in this register are written to TGRB_4. * Temporary registers 1, 2, and 3 (Temp1, 2, and 3) Temporary registers 1, 2, and 3 are between the respective buffer and comparison registers. Data written in a buffer register are transferred to the corresponding temporary register and then to the comparison register. The temporary registers cannot be accessed by the CPU. * Timer counter _3 (TCNT_3) TCNT_3 is a 16-bit counter. TCNT_3 decrementation on compare matches with TGRA_3, and incrementation on compare matches with the timer dead-time data register (TDDR). * Timer counter _4 (TCNT_4) TCNT_4 is a 16-bit counter. TCNT_4 decrementation on compare matches with the timer cycle data register (TCDR), and incrementation when timer counting reaches H'0000. * Timer dead time data register (TDDR) The TDDR is a 16-bit readable and writable register. The dead time for the PWM waveforms is set in this register. * Timer cycle data register (TCDR) The TCDR is a 16-bit register. The setting in this register defines half of the cycle for the PWM carrier. * Timer cycle buffer register (TCBR) The TCBR functions as the buffer register for the TCDR. During timer operation, the values set in this register are written to TCDR.
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MTU2: Output of Complementary Pairs of PWM Signals in Three Phases (Complementary PWM Mode)
2.2
2.2.1
Operation of the Sample Program
Settings for Operation of the Sample Program
In this sample program, the output of complementary PWM waveforms in three phases on channels 3 and 4 of MTU2 is obtained by selecting complementary PWM mode 3. An output level is also toggled in synchronization with the PWM carrier cycle. Table 3 gives the setting conditions for operation in complementary PWM mode in this sample program. Figure 4 shows a sample of output waveforms in complementary PWM mode. Table 3 Setting for Operation in Complementary PWM Mode Description 3 and 4 Complementary PWM mode 3 (data transfer at the crest and trough of the counter value) * TIOC3A pin: Output toggled in synchronization with the PWM cycle * TIOC3B pin: PWM output 1 (positive waveform) * TIOC3D pin: PWM output 1' (inverse waveform for PWM output 1) * TIOC4A pin: PWM output 2 (positive waveform) * TIOC4C pin: PWM output 2' (inverse waveform for PWM output 2) * TIOC4B pin: PWM output 3 (positive waveform) * TIOC4D pin: PWM output 3' (inverse waveform for PWM output 3) * Output of positive signal: Active low * Output of inverse signal: Active low 10 MHz (Obtained by dividing P clock frequency by 4) 400 s (carrier frequency: 2.5 kHz) 4 s * Initial duty cycle for PWM outputs 1, 2, 3: 50% PWM duty cycle value is updated every time the TGRA_3 interrupt is generated (setting is incremented or decremented). * Compare match interrupt for TGRA_3 A TGRA_3 compare match is generated once per PWM-carrier cycle.
Item Channels in use Operating mode Functions of pins
Active level Counter clock PWM carrier cycle Short-circuit prevention interval (dead time) PWM duty cycle
Interrupt
PWM carrier cycle TIOC3A pin (Toggled output) 1 0
PWM carrier cycle
Short-circuit prevention interval
Short-circuit prevention interval
TIOC3B pin (PWM output 1, positive) TIOC3D pin (PWM output 1', inverse) TIOC4A pin (PWM output 2, positive) TIOC4C pin (PWM output 2', inverse) TIOC4B pin (PWM output 3, positive) TIOC4D pin (PWM output 3', inverse)
1 0 1 0
1 0 1 0 1 0 1 0
PWM waveform outputs are active low level (for both phases of each pair). : Active level (low)
Figure 4 Output Waveforms in Complementary PWM Mode Operation
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2.2.2
Description of Operation by the Sample Program
1. Operation of Timer Counters Figure 5 shows the operation of two timer counters in complementary PWM mode. Counters TCNT_3 and TCNT_4 of channels 3 and 4 count up and then down. The initial setting of the TCNT_3 counter is the same as the value set in the TDDR. The initial setting of the TCNT_4 counter is H'0000. Timer counting starts simultaneously on channels 3 and 4.
TCNT_3 and TCNT_4 Switched to down-counting on a compare match with TGRA_3. TGRA_3 TCDR TCNT_3 Switched to down-counting on a compare match with TCDR.
TCNT_4 TDDR H'0000 Counting starts. Switched to up-counting on a compare match with H'0000. Switched to up-counting on a compare match with TDDR.
Figure 5 Operation of Timer Counters 2. PWM Waveform Output The output of complementary PWM waveforms in three phases is controlled by timer counters (TCNT_3, TCNT_4) and comparison registers (TGRB_3, TGRA_4, TGRB_4). The counters for PWM output are constantly compared with the comparison registers (TGRB_3, TGRA_4, and TGRB_4). When the counter values match the values of these registers, the output levels of the positive and inverse PWM signals are switched according to the values of bits OLSN and OLSP in the timer output control register (TOCR). Figure 6 shows the output signals (the positive and inverse phases) for a single complementary pair. The output signal of the positive and inverse phases is controlled by timer counters (TCNT_3, TCNT_4) and compare match registers.
: TGRB_3 (comparison register) Value is changed for the timing of PWM output 1 and PWM output 1'. : Compare match with TGRB_3
TCNT_3 and TCNT_4 TGRA_3 TCDR TCNT_3 TCNT_4 TGRB_3 TCNTS
TDDR H'0000 Short-cut circuit prevention interval TIOC3B pin (PWM output 1, positive) TIOC3D pin (PWM output 1', inverse) 1 0 1 0 Output of the inverse signal is switched to 0 when counting down by TCNT_3 leads to a match with TGRB_3. Output of the positive signal is switched to 1 when counting down by TCNT_4 leads to a match with TGRB_3. Short-cut circuit prevention interval
Output of the inverse signal is switched to 1 when counting up by TCNT_3 leads to a match with TGRB_3. Output of the positive signal is switched to 0 when counting up by TCNT_4 leads to a match with TGRB_3.
PWM waveform outputs are active low level (for both phases of each pair). : Active level (low)
Figure 6 Output of PWM Waveforms in Complementary PWM Mode
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MTU2: Output of Complementary Pairs of PWM Signals in Three Phases (Complementary PWM Mode)
3. Changes to PWM Duty Cycle Figure 7 shows the timing of updating values for the PWM duty cycle. In this sample program, the register settings for PWM duty cycle are incremented or decremented from the handler for a compare-match interrupt with TGRA_3 (that generated at the highest counter value). Changes to three buffer registers TGRD_3, TGRC_4, and TGRD_4 are used to increment or decrement the values of PWM duty cycle. When the duty cycle is changed, make sure that the last setting to be made is that for TRGR_4. Furthermore, if the value in TGRD_4 is neither incremented nor decremented, make sure that a value is written to TGRD_4 after the registers with values to be incremented or decremented have been updated.
: TGRD_3 (buffer register) : temp (temporary register for TGRB_3) : TGRB_3 (comparison register) : Comparison register of TGRB_3 TCNTS TCNT_3 TCNT_4 TGRD_3 TGRB_3
TCNT_3 and TCNT_4 TGRA_3 TCDR
TDDR H'0000 TGRA_3 interrupt flag TGRA_3 interrupt processing (data update) TGRD_3 buffer register Temporary register TGRB_3 compare register data 1 data 1 data 1 *: mode PWM mode 3 (transfer at crest and trough)
Incrementation/decrementation of register value (data 2) data 2 data 2 (data 1) (data 2) data 2
Incrementation/decrementation of register value (data 3) data 3 data 3 (data 2) (data 3) data 3
Figure 7 Timing of Updating the PWM Duty Cycle 4. Output Toggling in Synchronization with the PWM Cycle Figure 8 shows the operations for toggling of an output level in synchronization with the PWM cycle. The PSYE bit in the timer output control register (TOCR) is set to 1 to select toggling of an output in synchronization with the PWM carrier cycle. Toggling is of the signal on the TIOC3A pin. The initial value for output is 1.
TCNT_3 and TCNT_4 TGRA_3 TCDR TCNT_3 Output level is toggled on a compare match with H'0000.
TCNT_4 TDDR H'0000 Carrier cycle TIOC3A pin 1 (toggled output) 0
Output level is toggled on a compare match with H'0000.
Figure 8 Operation for Toggling an Output in Synchronization with the PWM Cycle
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2.2.3
Examples of Output with Desired PWM Duty Cycles
Table 4 gives relations between register settings for PWM duty cycle and the behavior of the positive and inverse waveforms in one phase. In complementary PWM mode, when the value in a comparison register (TGRB_3, in this sample program) is H'0000, the positive output remains ON while the inverse output remains OFF; i.e. the output levels are fixed. Furthermore, when the value in the comparison register is greater than or equal to the value in the TGRA_3 register, the level of the positive signal is fixed to the OFF state while the level of the inverse signal is fixed to the ON state. Figures 9 and 10 shows examples of output waveforms of the positive and inverse signals. When changing the PWM duty cycle, make sure that the values are set in the corresponding buffer registers rather than directly in the comparison registers and that changing comparison registers should be made via the buffer registers. Table 4 Examples of Setting that Control the PWM Duty Cycle and Output Waveforms Output Waveforms*1 Positive output (TIOC3B pin) Fixed to the OFF state (high) Fixed to the OFF state (high) Fixed to the OFF state (high) Inverse output (TIOC3D pin) Fixed to the ON state (low) Output of the OFF waveform (pulse) Output of the OFF waveform (to be a pulse twice the width of the short-circuit prevention interval) Output of the OFF waveform Waveform Chart Figure 9 (a) -- Figure 9 (b)
Value in TGRB_3 TGRB_3 TGRA_3 Between TGRA_3 and TCDR TGRB_3 = TCDR
Between (TCDR - Td) and TCDR TGRB_3 = (TCDR - Td)
Between (TDDR x 2) and (TCDR - Td) TGRB_3 = (TDDR x 2)
Output of the ON waveform (pulse) Output of the ON waveform Output of the OFF waveform (to be a pulse twice the (to be a pulse four times the width of the short-circuit width of the short-circuit prevention interval) prevention interval) Output of complementary PWM waveforms Output of the OFF waveform (to be a pulse four times the width of the short-circuit prevention interval) Output of the OFF waveform Output of the OFF waveform (to be a pulse twice the width of the short-circuit prevention interval) Output of the OFF waveform (pulse) Fixed to the ON state (low) Output of the ON waveform (to be a pulse twice the width of the short-circuit prevention interval) Output of the ON waveform (pulse) Fixed to the OFF state (high)
-- Figure 9 (c)
-- Figure 10 (a)
Between TDDR and (TDDR x 2) TGRB_3 = TDDR
-- Figure 10 (b)
Between H'0000 and TDDR TGRB_3 = H'0000
Fixed to the OFF state (high)
--
Figure 10 (c) Fixed to the OFF state (high) Note: 1. The active level of the PWM output is set to low. The descriptions of the output waveforms refer to the positive and inverse signals for a single complementary pair.
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MTU2: Output of Complementary Pairs of PWM Signals in Three Phases (Complementary PWM Mode)
(a) TGRB_3 = TGRA_3 TCNT_3 and TCNT_4 TGRB_3 (= TGRA_3) TGRA_3 TCDR Td TCNTS TGRB_3: Value of comparison register : Active level (low) Td: Short-circuit prevention interval setting
TCNT_3 TCNT_4 TDDR H'0000
TIOC3B pin (PWM output 1, positive) TIOC3D pin (PWM output 1', inverse phase) (b) TGRB_3 = TCDR
1 0 1 0
Fixed to OFF (high) Fixed to ON (low)
TCNT_3 and TCNT_4 TGRA_3 TGRB_3 (= TCDR) TCDR Td TCNTS
TCNT_3 TCNT_4 TDDR H'0000 Short-circuit prevention interval 1 0 1 0 Fixed to OFF (high) ON (low) OFF OFF Short-circuit prevention interval Short-circuit prevention interval Short-circuit prevention interval
TIOC3B pin (PWM output 1, positive) TIOC3D pin (PWM output 1', inverse phase) (c) TGRB_3 = TCDR - Td
TCNT_3 and TCNT_4 TGRA_3 TCDR TGRB_3 (= TCDR - Td) Td Td TCNTS
TCNT_3
TCNT_4 TDDR H'0000 Short-circuit prevention interval 1 0 1 0 OFF (high) ON (low) ON OFF Short-circuit prevention interval OFF OFF
TIOC3B pin (PWM output 1, positive) TIOC3D pin (PWM output 1', inverse phase)
Figure 9 Examples of PWM Waveform Output (1)
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(a) TGRB_3 = 2 x TDDR TCNT_3 and TCNT_4 TGRA_3 TCDR TCNTS TGRB_3: Value of comparison register : Active level (low) Td: Short-circuit prevention interval setting
TCNT_3 TCNT_4 TGRB_3 (= 2 x TDDR) TDDR H'0000 Td Td
TIOC3B pin (PWM output 1, positive) TIOC3D pin (PWM output 1', inverse phase)
1 0 1 0
OFF
ON
OFF
OFF
ON
OFF
ON
ON
(b) TGRB_3 = TDDR
TCNT_3 and TCNT_4 TGRA_3 TCDR TCNTS
TCNT_3 TCNT_4 TGRB_3 (= TDDR) TDDR Td H'0000
TIOC3B pin (PWM output 1, positive) TIOC3D pin (PWM output 1', inverse phase) (c) TGRB_3 = H'0000
1 0 1 0 Fixed to OFF (high)
ON
OFF
ON
OFF
TCNT_3 and TCNT_4 TGRA_3 TCDR TCNTS
TGRB_3: Value of comparison register
TCNT_3 TCNT_4 TDDR TGRB_3 (= H'0000) H'0000 Td
TIOC3B pin (PWM output 1, positive) TIOC3D pin (PWM output 1', inverse phase)
1 0 1 0
Fixed to ON (low)
Fixed to OFF (high)
Figure 10 Examples of PWM Waveform Output (2)
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MTU2: Output of Complementary Pairs of PWM Signals in Three Phases (Complementary PWM Mode)
2.3
2.3.1
Configuration of the Sample Program
Description of Functions
Table 5 lists functions used in this sample program.
Table 5
Functions Used Label main () stbcr_init () mtu2_init () pfc_init () Description Initializes other modules and makes settings for timers of MTU2 Makes setting to release MTU2 from standby Initializes MTU2 (channels 3 and 4) Places channels 3 and 4 in complementary PWM mode 3 Initializes the pin function controller (PFC) Selects the required MTU2-related pin functions, so that the pins function as timer pins Handles the TGRA_3 compare match interrupt from MTU2 (channel 3) Increments or decrements the setting to control the threephase PWM duty cycle Generates an interrupt for every cycle of the PWM carrier cycle (400 s)
Function Name Main Standby setting Initialization of MTU2 Initialization of PFC
TGRA_3 interrupt
int_mtu2_tgia3 ()
2.3.2
Variable Usage
Table 6 gives a list of variables used in the sample program. Table 6 Variable Usage Description Name of Employing Module mtu2_init ()
Label Name
Dead_time C_cycle Pul_cycle Pul_pwm_duty1
Pul_pwm_duty2
Pul_pwm_duty3
Setting for dead time (value set in the TDDR) 1/2 the PWM carrier cycle (value set in the TCBR) 1/2 the PWM carrier cycle + value of dead time (value set in the TGRC_3) PWM duty-cycle setting for the PWM1 output (pins TIOC3B and TIOC3D) (value set in the TGRD_3) PWM duty-cycle setting for the PWM2 output (pins TIOC4A and TIOC4C) (value set in the TGRC_4) PWM duty-cycle setting for the PWM3 output (pins TIOC4B and TIOC4D) (value set in the TGRD_4)
mtu2_init () int_mtu2_tgia3 ()
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2.4
Procedure for Setting the Module Used
The following subsections describe the flow of processing by the sample program.
2.4.1
Main Function
Figure 11 shows the flow of processing by the main function.
main()
0Duty_select
[1]
[1] Variable initialization Flag (Duty_select) to judge the need to update the PWM duty cycle is initialized. [2] On-chip peripheral modules are released from standby
Initialization: release from standby stbcr_init()
[2]
Initialization: MTU2 mtu2_init()
[3]
[3] Initialization of multi-function timer pulse unit 2 (MTU2)
Set interrupt priority register E (IPRE)
[4]
[4] Interrupt controller (INTC) setting Interrupt priority level of the interrupt sources (TGI3A to TGI3D) from MTU2 is set to D'15 (H'F). [5] Initialization of pin function controller (PFC) [6] Setting for timer start register (TSTR) of MTU2 * CST4 bit = B'1: Specifies counting by timer counter TCNT_4. * CST3 bit = B'1: Specifies counting by timer counter TCNT_3. The CST3 and CST4 bits are set simultaneously. [7] Setting the interrupt mask bit to 0 CPU interrupts at all interrupt priority levels are enabled.
Initialization: PFC pfc_init()
[5]
Set timer start register (TSTR)
[6]
Release interrupt mask set_imask(0)
[7]
Figure 11 Processing by Function main
2.4.2
Initialization for Standby
Figure 12 shows the flow of processing for standby processing.
stbcr_init()
Set standby control register 3 (STBCR3)
[1]
[1] Release of the module from standby * MSTP35 bit = B'0: Clock supply to MTU2 is enabled.
END
Figure 12 Initialization: Release from Standby
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2.4.3
Initialization of Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 13 shows the flow for initialization of MTU2. Settings are made to set up complementary PWM mode 3 on channels 3 and 4.
mtu2_init()
Initialize variables
[1]
[1] Initialization of variables for use in setting the PWM cycle, dead time, and PWM duty cycle [2] Clear bits CST3 and CST4 in timer start register (TSTR) to 0 to halt counting by the timer counters (TCNT).
Set timer start register (TSTR)
[2]
Set timer control register_3 (TCR_3) and timer control register_4 (TCR_4)
[3]
Set timer counter_3 (TCNT_3) and timer counter_4 (TCNT_4)
[3] Specification of clock source and source for clearing of timer counters * CCLR[2:0] bits = B'000: Disables clearing of TCNT. * CKEG[1:0] bits = B'00: TCNT counts rising edges. * TPSC[2:0] bits = B'001: TCNT counts cycles of internal clock P/4. The same initial values are set in registers TCR_3 and TCR_4. [4] Initialization of timer counters TCNT_3 and TCNT_4 * Value of dead time is set in the TCNT_3 register. * H'0000 is set in the TCNT_4 register.
[4]
Set the following registers: timer general register B_3 (TGRB_3), buffer register D_3 (TGRD_3), timer general register A_4 (TGRA_4), buffer register C_4 (TGRC_4), timer general register B_4 (TGRB_4), and buffer register D_4 (TGRD_4)
[5]
[5] Initialization of PWM duty cycles Initial values for PWM duty cycle are set in compare match registers (TGRB_3, TGRA_4, and TGRB_4) and buffer registers (TGRD_3, TGRC_4, and TGRD_4). The same values are set in the compare match registers and buffer registers.
[6] The value (1/2 the carrier cycle + dead time) is set in the TGRA_3 register and in buffer register TGRC_3. Set timer general register A_3 (TGRA_3) and timer general register C_3 (TGRC_3) [6] [7] Value of dead time is set in the dead time data register (TDDR). [8] Half the carrier cycle is set in the timer cycle data register (TCDR) and timer cycle buffer register (TCBR). When the setting for non-generation of dead time has been made, set TDDR to 1, and TGRA_3 and TGRC_3 to the value (1/2 the carrier cycle + 1).) [9] Using the PSYE bit in timer output control register (TOCR1) to specify enabling or disabling of output toggling in synchronization with the PWM cycle; PWM output level setting by the OLSP and OLSN bits * PSYE bit = B'1: Enable toggled output. * OLSN bit = B'0: Inverse output is active at the low level. * OLSP bit = B'0: Output of positive signals is active at the low level. [10] Setting to complementary PWM mode 3 by timer mode register_3 (TMDR_3) * MD[3:0] bits = B'1111: Complementary PWM mode 3 (transfer at crest and trough) Do not make any setting in the TMDR_4 register. Additionally, mode setting should be made while TCNT_3 and TCNT_4 are halted. [11] Using timer output master enable register (TOER) to enable output on PWM output pins [12] Setting to enable or disable interrupt requests * TGIEA bit = B'1: Enables interrupt requests (TGIA_3) from channel 3 corresponding to setting of the TGFA bit.
Set timer dead time data register (TDDR)
[7]
Set timer cycle data register (TCDR) and timer cycle buffer register (TCBR)
[8]
Set timer output control register 1 (TOCR1) Set timer mode register_3 (TMDR_3) Set timer output master enable register (TOER)
[9]
[10]
[11]
Set timer interrupt enable register_3 (TIER_3)
[12]
END
Figure 13 Initialization of MTU2
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MTU2: Output of Complementary Pairs of PWM Signals in Three Phases (Complementary PWM Mode)
2.4.4
Initialization of Pin Function Controller (PFC)
Figure 14 shows the flow for initialization of the PFC.
pfc_init()
Set port E control register L4 (PECRL4) Set port E control register L3 (PECRL3)
[1]
[1] Setting functions of multiplexed pins on port E * PE15MD[2:0] bits = B'110: Specifies the TIOC4D function (MTU2) for PE15. * PE14MD[2:0] bits = B'110: Specifies the TIOC4C function (MTU2) for PE14. * PE13MD[2:0] bits = B'110: Specifies the TIOC4B function (MTU2) for PE13. * PE12MD[2:0] bits = B'110: Specifies the TIOC4A function (MTU2) for PE12. [2] Setting functions of multiplexed pins on port E * PE11MD[2:0] bits = B'110: Specifies the TIOC3D function (MTU2) for PE11. * PE9MD[2:0] bits = B'110: Specifies the TIOC3B function (MTU2) for PE9. * PE8MD[2:0] bits = B'110: Specifies the TIOC3A function (MTU2) for PE8. [3] Setting input and output directions for port E pins (PE15 to PE0) * PE15IOR bit = B'1: Specifies the TIOC4D pin (PE15) for output. * PE14IOR bit = B'1: Specifies the TIOC4C pin (PE14) for output. * PE13IOR bit = B'1: Specifies the TIOC4B pin (PE13) for output. * PE12IOR bit = B'1: Specifies the TIOC4A pin (PE12) for output. * PE11IOR bit = B'1: Specifies the TIOC3D pin (PE11) for output. * PE9IOR bit = B'1: Specifies the TIOC3B pin (PE9) for output. * PE8IOR bit = B'1: Specifies the TIOC3A pin (PE8) for output.
[2]
Set port E I/O register L (PEIORL)
[3]
END
Figure 14 Initialization of Pin Function Controller (PFC)
2.4.5
Handling of the Compare Match Interrupt
Figure 15 shows the flow for handling the compare match interrupt (TGRA_3) from MTU2.
int_mtu2_tgia3() [1] Clearing an interrupt source flag * TGFA bit = B'0: Compare flag A of timer status register_3 (TSR_3) is cleared. To clear the flag, write 0 to this bit after having read it as 1.
Clear interrupt flag of TGRA_3 [2] Pul_pwm_duty1 == 0?
[1]
No [3] Is Pul_pwm_duty1 greater than the PWM cycle? Yes No [2] [3] Setting flags Flag (the variable Duty_select) to judge the need to increment or decrement of the PWM duty cycle is set. * If the duty cycle is 0, the setting for incrementation is made (0Duty_select). * If the duty cycle is greater than the PWM cycle, the setting for decrementation is made (1Duty_select).
Yes
0Duty_select Setting for incrementation [4] Duty_select == 0? Yes Incrementation of settings for duty cycle Pul_pwm_duty1 ++ Pul_pwm_duty2 ++ Pul_pwm_duty3 ++ No
1Duty_select Setting for decrementation
[4] Flag judgment Settings for PWM duty cycle are incremented or decremented. Decrementation of settings for duty cycle Pul_pwm_duty1 -- Pul_pwm_duty2 -- Pul_pwm_duty3 --
Pul_pwm_duty1TGRD_3 Pul_pwm_duty2TGRC_4 Pul_pwm_duty3TGRD_4 END
[5]
[5] Setting PWM duty cycle in registers * Buffer register TGRD_3: Duty cycle for PWM1 output (positive/inverse) is set. * Buffer register TGRC_4: Duty cycle for PWM2 output (positive/inverse) is set. * Buffer register TGRD_4: Duty cycle for PWM3 output (positive/inverse) is set.
Figure 15 Interrupt Handling
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2.5
Settings of Registers in the Sample Program
The following describes the settings of registers used in the sample program.
2.5.1
Clock Pulse Generator (CPG)
Table 7 gives a list of settings for registers of the clock pulse generator (CPG). Table 7 Clock Pulse Generator (CPG) Address H'FFFFE800 Setting H'0241 Description Specifies division ratios for operating frequency * IFC[2:0] = B'000: x1, internal clock (I) * BFC[2:0] = B'001: x1/2, bus clock (B) * PFC[2:0] = B'001: x1/2, peripheral clock (P) * MIFC[2:0] = B'000: x1, MTU2S clock (MI) * MPFC[2:0] = B'001: x1/2, MTU2 clock (MP)
Register Name Frequency control register (FRQCR)
2.5.2
Power-Down Modes
Table 8 gives register settings related to low-power modes. Table 8 Power-Down Modes Address H'FFFFE808 Setting H'BF Description Settings for the operation of various modules * MSTP23 = B'1: Clock supply to MTU2S halted. * MSTP22 = B'0: MTU2 runs. * MSTP21 = B'1: Clock supply to CMT halted. * MSTP20 = B'1: Clock supply to A/D_1 halted. * MSTP19 = B'1: Clock supply to AD_0 halted.
Register Name Standby control register 4 (STBCR4)
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2.5.3
Multi-Function Timer Pulse Unit 2 (MTU2)
Table 9 gives a list of settings for registers of multi-function timer pulse unit 2 (MTU2). Table 9 Multi-Function Timer Pulse Unit 2 (MTU2) Address H'FFFFC200 Setting H'01 Description Sets details of TCNT control. * CCLR[2:0] = B'000: TCNT clearing disabled * CKEG[1:0] = B'00: TCNT counts rising edge. * TPSC[2:0] = B'001: TCNT counts cycles of internal clock P/4. Sets details of TCNT control. * CCLR[2:0] = B'000: TCNT clearing disabled * CKEG[1:0] = B'00: TCNT counts rising edge. * TPSC[2:0] = B'001: TCNT counts cycles of internal clock P/4. 16-bit counter For complementary PWM mode, the initial value is the same as the value in timer dead time data register (TDDR). 16-bit counter Initial value is set to H'0000. For complementary PWM mode, sets the upper limit (1/2 carrier cycle + dead time) of TCNT_3. For complementary PWM mode, a buffer register for TGRA_3. The initial value is the same as the value in TGRA_3. For complementary PWM mode, a comparison register for PWM output 1. Determines the PWM duty cycle (initial output value). In complementary PWM mode, a buffer register for TGRB_3 The initial value is the same as the value in the TGRB_3. Incremented or decremented value of PWM duty cycle is set in this register For complementary PWM mode, a comparison register for PWM output 2. Determines the PWM duty cycle (initial output value). In complementary PWM mode, a buffer register for TGRA_4. The initial value is the same as the value in TGRA_4. Incremented or decremented value of PWM duty cycle is set in this register.
Register Name Timer control register_3 (TCR_3)
Timer control register_4 (TCR_4)
H'FFFFC201
H'01
Timer counter_3 (TCNT_3)
H'FFFFC210
D'40
Timer counter_4 (TCNT_4) Timer general register A_3 (TGRA_3) Timer general register C_3 (TGRC_3)
H'FFFFC212 H'FFFFC218 H'FFFFC224
H'0000 D'2040
Timer general register B_3 (TGRB_3)
H'FFFFC21A
D'1020
Timer general register D_3 (TGRD_3)
H'FFFFC226
Timer general register A_4 (TGRA_4)
H'FFFFC21C
D'1020
Timer general register C_4 (TGRC_4)
H'FFFFC228
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Register Name Timer general register B_4 (TGRB_4) Timer general register D_4 (TGRD_4)
Address H'FFFFC21E
Setting D'1020
Description For complementary PWM mode, a comparison register for PWM output 3. Determines the PWM duty cycle (initial output value). In complementary PWM mode, a buffer register for the TGRB_4. The initial value is the same as the value in TGRB_4. Incremented or decremented value of PWM duty cycle is set in this register. 16-bit register used only in complementary PWM mode. Sets the offset value (the dead time) between TCNT_4 and TCNT_3. Register used only in complementary PWM mode. Sets the upper limit (1/2 the carrier cycle) of TCNT_4. Register used only in complementary PWM mode. Buffer register for the TCDR. Sets the same as the value in TCDR. Sets output operation in complementary PWM mode. * PSYE = B'1: Toggled output in synchronization with the PWM cycle is enabled. * TOCL = B'0: Writing to the TOCS, OLSN, and OLSP bits is enabled. * TOCS = B'0: Selects use of the TOCR1 setting * OLSN = B'0: Selects levels for inverse output in complementary PWM mode. Initial output = high, active level = low * OLSP = B'0: Selects levels for output of positive signals in complementary PWM mode. Initial output = high, active level = low Sets operation mode (channel 3). * BFB = B'1: TGRB and TGRD are used together (buffered operation) * BFA = B'1: TGRA and TGRC are used together (buffered operation) * MD[3:0] = B'1111: Complementary PWM mode 3 (transfer at crest and trough)
H'FFFFC22A
Timer dead time data register (TDDR) Timer cycle data register (TCDR) Timer cycle buffer register (TCBR) Timer output control register 1 (TOCR1)
H'FFFFC216
D'40
H'FFFFC214 H'FFFFC222
D'2000
H'FFFFC20E
H'40
Timer mode register_3 (TMDR_3)
H'FFFFC202
H'3F
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Register Name Timer mode register_4 (TMDR_4)
Address H'FFFFC203
Setting --
Description Sets operation mode (channel 4). Note: When channel 3 is set to complementary PWM mode, settings made for channel 4 are ineffective (operation is automatically in accord with the settings of channel 3). No setting is made; the register is left at its initial value. Specifies enabling or disabling of output through the MTU2 output pins. * OE4D = B'1: MTU2 output on the TIOC4D pin is enabled. * OE4C = B'1: MTU2 output on the TIOC4C pin is enabled. * OE3D = B'1: MTU2 output on the TIOC3D pin is enabled. * OE4B = B'1: MTU2 output on the TIOC4B pin is enabled. * OE4A = B'1: MTU2 output on the TIOC4A pin is enabled. * OE3B = B'1: MTU2 output on the TIOC3B pin is enabled. Specifies enabling or disabling of interrupt requests. * TGIEA = B'1: Interrupt requests (TGIA) corresponding to setting of the TGFA bit are enabled. Selects operation or stoppage of TCNT for channels 0 to 4. * CST4 = B'1: TCNT_4 counts * CST3 = B'1: TCNT_3 counts Counting by TCNT_2 to TCNT_0 is stopped. Bit settings for counting by TCNT_4 and TCNT_3 should be made at the same time.
Timer output master enable register (TOER)
H'FFFFC20A
H'FF
Timer interrupt enable register_3 (TIER_3)
H'FFFFC208
H'01
Timer start register (TSTR)
H'FFFFC280
H'C0
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2.5.4
Interrupt Controller (INTC)
Table 10 gives a list of settings for registers of the interrupt controller (INTC). Table 10 Interrupt Controller (INTC) Register Name Interrupt priority register E (IPRE) Address H'FFFFE984 Setting H'00F0 Description Selects interrupt priority (level 0 to 15). * Bit 15 to 12 = B'0000: MTU2 (TGIA_2 and TGIB_2) interrupt level = 0 * Bit 11 to 8 = B'0000: MTU2 (TCI2V and TCI2U) interrupt level = 0 * Bit 7 to 4 = B'1111: MTU3 (TGI3A to TGI3D) interrupt level = 15 * Bit 3 to 0 = B'0000: MTU3 (TCIV_3) interrupt level = 0 In this sample program, TGI3A interrupt is used.
2.5.5
Pin Function Controller (PFC)
Table 11 gives a list of settings for registers of the pin function controller (PFC). Table 11 Pin Function Controller (PFC) Register Name Port E control register L4 (PECRL4) Address H'FFFFD310 Setting H'1111 Description Specifies functions of multiplexed pins on port E. * PE15MD[2:0] = B'001: Specifies the TIOC4D I/O (MTU2) for PE15. * PE14MD[2:0] = B'001: Specifies the TIOC4C I/O (MTU2) for PE14. * PE13MD[2:0] = B'01: Specifies the TIOC4B I/O (MTU2) for PE13. * PE12MD[2:0] = B'001: Specifies the TIOC4A I/O (MTU2) for PE12. Specifies functions of multiplexed pins on port E. * PE11MD[2:0] = B'001: Specifies the TIOC3D I/O (MTU2) for PE11. * PE10MD[2:0] = B'000: Specifies the PE10 I/O (port) for PE10. * PE9MD[2:0] = B'001: Specifies the TIOC3B I/O (MTU2) for PE9. * PE8MD[2:0] = B'001: Specifies the TIOC3A I/O (MTU2) for PE8. Specifies input and output directions for port E pins. * PE15IOR = B'1: Specifies the TIOC4D pin (PE15) for output. * PE14IOR = B'1: Specifies the TIOC4C pin (PE14) for output. * PE13IOR = B'1: Specifies the TIOC4B pin (PE13) for output. * PE12IOR = B'1: Specifies the TIOC4A pin (PE12) for output. * PE11IOR = B'1: Specifies the TIOC3D pin (PE11) for output. * PE10IOR = B'0: Specifies the PE10 (port) for input. * PE9IOR = B'1: Specifies the TIOC3B pin (PE9) for output. * PE8IOR = B'1: Specifies the TIOC3A pin (PE8) for output. * PE7IOR to PE0IOR all set to B'0: PE7 to PE0 are input pins.
Port E control register L3 (PECRL3)
H'FFFFD312
H'1011
Port E I/O register L (PEIORL)
H'FFFFD306
H'FB00
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3.
Documents for Reference
* Hardware Manual SH7137 Group Hardware Manual (REJ09B0402) The most up-to-date version of this document is available on the Renesas Technology Website. * Software Manual SH-1/SH2/SH-DSP Software Manual (REJ09B0171) The most up-to-date version of this document is available on the Renesas Technology Website.
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Website and Support
Renesas Technology Website http://www.renesas.com/ Inquiries http://www.renesas.com/inquiry csc@renesas.com
Revision Record
Rev. 1.00 Date Jun.03.09 Description Page Summary -- First edition issued
All trademarks and registered trademarks are the property of their respective owners.
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Notes regarding these materials
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